1. Field of the Invention
The present invention relates to a wiring board such as a printed wiring board, in particular, to a hybrid wiring board that is a combination of a rigid wiring substrate and a flexible wiring substrate.
In addition, the present invention relates to a flexible wiring substrate of which a wiring layer is disposed on insulation resin film, in particular, to a flexible wiring substrate laminated with a rigid wiring substrate.
Furthermore, the present invention relates to a semiconductor apparatus such as a semiconductor package of which a semiconductor device is mounted on a printed wiring board, in particular, to a semiconductor apparatus that mounts a semiconductor device with connection terminals disposed at a high mounting density.
Moreover, the present invention relates to a fabrication method of a printed wiring board, in particular, to a fabrication method of a hybrid wiring board that is a combination of a rigid wiring substrate and a flexible wiring substrate.
2. Description of the Related Art
The degree of integration of semiconductor devices is increasing year by year. Thus, the number of connection terminals (pads) for connecting a semiconductor device and an external circuit increases and the mounting density thereof becomes high. When the minimum machining size on a semiconductor device made of silicon or the like is around 0.2 .mu.m, as many as 1000 connection terminals should be disposed for a semiconductor device in a square shape whose one side is 10 mm.
Moreover, in a semiconductor apparatus such as a semiconductor package of which such a semiconductor device is mounted on a wiring board, to improve the mounting density, there are strong needs for reducing the size and thickness thereof. In particular, for a portable information unit such as a note type PC (Personal Computer), a PDA, or a portable telephone unit, it is important to decrease the size and thickness of a semiconductor package.
To package a semiconductor device, it is necessary to mount a semiconductor device on a wiring board and connect terminals of the semiconductor device and the wiring board. However, to dispose around 1000 connection terminals around a semiconductor device in a square shape whose one side is around 10 mm, the mounting pitches of the connection terminals become as small as around 40 .mu.m. To connect terminals disposed at fine pitches to terminals of a wiring board, high accuracy is required in forming a circuit pattern and aligning wires. However, conventional wire bonding technologies and TAB (Tape Automated Bonding) technologies cannot satisfy such requirements.
As a conventional terminal connecting method, connection terminals of a semiconductor device and connection terminals of a wiring board may be connected through a pillar made of a conductive substance such as solder. For example, when connection terminals of 32 lines.times.32 rows at pitches of 32 .mu.m are disposed on a semiconductor device in a square shape whose one side is around 10 mm, the number of connection terminals amounts to as many as 1024.
Wires of a wiring board on which a semiconductor device is mounted are disposed at an L/S ratio (Line/Space, wiring width/wiring pitch) of as fine as around 50 .mu.m/50 .mu.m so as to connect the connection terminals of the semiconductor device and the external connection terminals of the semiconductor package.
As a wiring board for mounting a semiconductor device with connection terminals disposed at fine mounting pitches, for example a build-up board 900a shown in FIG. 10 has been used.
FIG. 10 is a sectional view showing the structure of a build-up board. The build-up board is a wiring board that has a printed wiring substrate 901, thin resin layers 902, and conductor wiring patterns 903. The printed wiring substrate 901 is a rigid board. The thin resin layers 902 are coated on both surfaces of the printed wiring substrate 901. The conductor wiring patterns 903 are made of metal or the like and disposed on the resin layers 902.
The printed wiring substrate 901 of the build-up board is referred to as core layer. The portions layered on both the surfaces of the core layer are referred to as build-up layers.
The insulation resin layers that structure the build-up layers are connected by a fine layer connecting means formed by photolithography technology or the like. A plurality of wiring layers are connected through the fine layer connecting means. In the example shown in FIG. 10, the layer connecting means of the build-up layers is accomplished by a photo via-hole 904.
To connect the wiring layers on the build-up layers (disposed on both the surfaces of the core layer), for example a through-hole 905 may be formed. To allow a wiring substrate to be flat, a build-up board of which the through-hole is filled with resin is known.
In the technology at the time the present invention was filed, the minimum wiring width of the wiring layer 903 that structures the build-up layers is around 40 .mu.m. The front surface of the insulation resin layer 902 is uneven due to a wiring pattern of a lower layer. Thus, it is very difficult to form a finer wiring pattern than the uneven surface.
The diameter of via-holes formed in the insulation resin layers 902 that structure the build-up layers is around 80 .mu.m. To form finer via-holes, the thickness of the insulation resin layers 902 may be decreased. When the thickness of the insulation resin layers 902 is decreased, the influence of the uneven surface of the lower layer becomes strong. Thus, the wiring width should be increased.
In addition, the thickness of the build-up board is restricted. To prevent the build-up board from deforming and breaking in and after the fabrication process, the build-up board should have a thickness of at least 0.6 mm. The thickness of each of the insulation resin layers 902 is in the range from around 30 to 50 .mu.m. The thickness of the conductor wiring layer 903 is in the range from around 10 to 20 .mu.m. To dispose around 1000 connection terminals, three wiring layers are required. Thus, the thickness of the build-up board becomes as large as 0.84 to 1.02 mm.
In addition, the above-described semiconductor device is disposed on one surface of the build-up board. For example, solder balls are disposed in a two-dimensional grid shape on the other surface of the build-up board (the resultant package is referred to as BGA package).
To decrease the thickness of the BGA package, it is necessary to decrease the thickness of the above-described core layer or the build-up layers. However, when the thickness of the core layer is decreased, the reliability of the resultant semiconductor package deteriorates. In addition, it is difficult to form the build-up layers.
When the thickness of the build-up layers is decreased, it is difficult to form a wiring pattern at fine pitches. Thus, practically, it is very difficult to decrease the thickness of the build-up board to 0.8 mm or less.
To decrease the outer side of a semiconductor package, it is necessary to decrease the diameters and pitches of through-holes formed in a wiring board on which a semiconductor device is mounted.
Generally, as a material of an insulation resin layer that structures a core layer, a prepreg of which a glass cloth woven with glass fibers is impregnated with an insulation resin is used. In such a wiring board with a prepreg, the glass fibers and hardened insulation resin layer securely adhere.
However, when through-holes are formed in a wiring board by a drill or the like, the glass fibers are broken as well as the insulation resin. Moreover, in the vicinity of through-holes, the glass fibers separate from the insulation resin.
A plate layer is formed on the inner wall of a through-hole. When the plate layer is formed, if there is a portion of which the glass fibers separate from the insulation resin in the vicinity of the through-hole, a plate solution that contains metal ions permeates the portion. When the pitches of through-holes are decreased, the pitches of the separate portions of the glass fibers and the insulation resin become small. In this case, the conductive substance that permeates the separate portions deteriorates the insulation between the through-holes.
Thus, it is very difficult to mount a semiconductor device with connection terminals disposed at very fine pitches on a build-up board. In addition, to structure such a semiconductor device as a semiconductor package, it is difficult to use a build-up board.
On the other hand, a semiconductor package of which a semiconductor device is mounted on a film laminate substrate is known. The film laminate substrate is a laminate of a plurality of film substrates with wiring layers disposed through an insulation film made of for example polyimide.
FIGS. 11 and 12 are sectional views showing the structures of film laminate substrates.
As a practical example of the material of insulation film 902, polyimide with a high chemical resistance is used. As a practical example of the material of a wiring layer 903, copper is used.
In film laminate substrates 900b and 900c shown in FIGS. 11 and 12, unlike with the build-up board 900a that is uneven due to the wiring layer 903, since the front surface of the insulation film 902 is even, a fine wiring pattern can be formed.
To form a fine wiring pattern, it is necessary to decrease the thickness of the wiring layer 903. When the wiring layer 903 is made of copper foil with a thickness of around 15 to 18 .mu.m, an L/S ratio of 25 .mu.m/25 .mu.m can be accomplished. With a wiring layer made of copper foil with a thickness of round 10 .mu.m to 15 .mu.m, an L/S ratio of 20 .mu.m/20 .mu.m can be accomplished.
To connect the wiring layers 903 disposed on both the surfaces of the insulation film 902, fine via-holes 904 are formed in the insulation film. The via-holes are filled with a conductive material. When an insulation layer 902 is made of polyimide film with a thickness of around 50 .mu.m, via-holes 904 with a diameter of around 50 .mu.m can be formed by laser radiation or photochemical technology. To further decrease the diameters of the via-holes 904, the thickness of the insulation film 902 can be further decreased.
As a method for connecting the wiring layers 903 disposed on the insulation film 902, bumps made of copper or the like are formed on the wiring layers 903 by plating process. Bonding metal layers are formed on the bumps. The bumps are pressure-fitted to a wiring layer formed on the other insulation film through insulation film.
However, in such a layer connecting method, it takes a time to form the bumps. In addition, it takes a time to form a metal layer (pad) to be bonded to the bumps. Thus, in this method, the yield is low and thereby the fabrication cost is high.
Instead of bumps of copper, wiring layers may be connected with Pb/Sn type solder. In this case, when the solder is melted and connected to the wiring layers, the solder may adversely spread out. Thus, this method is not suitable for fine connections.
When a semiconductor package of which a semiconductor device is mounted on the front surface of a wiring board that is a laminate of a plurality of insulation film layers (made of polyimide) with wiring layers (the semiconductor package having BGA connection terminals on the rear surface) is mounted to a mother board, conductor balls that connect the semiconductor package and the mother board are stressed. Thus, sufficient connecting reliability cannot be obtained.
The mother board of the semiconductor package is a printed wiring board having an insulation resin layer of which a glass cloth is impregnated with glass epoxy or the like.
Nearly, at an ordinary temperature (25.degree. C.), the coefficient of thermal expansion of polyimide is around 8 ppm. On the other hand, the coefficient of thermal expansion of glass epoxy is in the range from around 14 to 17 ppm. Thus, at the ordinary temperature, the difference of the coefficients of thermal expansion between polyimide and glass epoxy is around 1.7 to 2.1 times. Consequently, the solder balls that connect the semiconductor package and the mother board are subject to large stress.
After the semiconductor package is mounted on the mother board, due to a temperature change in operation, much larger stress takes place in the solder balls. When such a load cumulates in the solder balls, they crack and thereby the connecting reliability largely deteriorates.
Since the thickness of the semiconductor device and the wiring board that structure the semiconductor package is decreased and there is the difference of the coefficients of linear expansion thereof, they are stressed. Thus, the connecting reliability deteriorates.
In the build-up board, when the thickness of the insulation layer is decreased so as to decrease the diameters of via-holes, it becomes difficult to finely form a wiring pattern. In addition, since through-holes of the core layer are formed by a drill, the diameters and pitches of the through-holes cannot be decreased. Moreover, when the thickness of the semiconductor package is decreased, the required strength cannot be obtained in the fabrication process, in particular, the build-up layer forming process.
In the case of a wiring board of which a plurality of film substrates with wiring layers are laminated on insulation film made of polyimide or the like, the yield is low and thereby the fabrication cost is high. In addition, since the difference of the coefficients of linear expansion of the material of the insulation film and the mother board on which the wiring board is disposed is large, the connecting reliability is low.
When a plurality of wiring substrates of same type or different type are laminated, the following problems take place.
There are technologies for laminating a plurality of wiring substrates (single-sided plate, double-sided plate, multi-layered plate, flexible substrate, or the like). As an example, a plurality of insulation layers having adhesive characteristic (for example, prepreg layers) are aligned through adhesive agent. The aligned substrates are pressured and heated. Thus, a laminated is mechanically formed. The laminate is drilled and plated so as to form PTHs (Plated Through-Holes). In such a manner, the layers are electrically connected.
A laminate of a plurality of rigid wiring substrates connected with PTHs or the like is referred to as IVH laminate wiring board.
A laminate of a rigid wiring substrate with layers connected with PTHs or the like and a flexible wiring substrate is referred to as rigid flexible substrate.
When a plurality of wiring substrates are laminated, through-holes should be formed by a number of processes such as the drilling process and the plating process. Thus, the yield is low.
In the plating process, waste fluid that adversely influences the environment is inevitable. To suppress the adverse influence of the waste fluid against the environment, a facility and time for processing the waste fluid are required. Thus, the yield becomes low and thereby the fabrication cost becomes high.
When layers are connected by the plating process, the thickness of conductor of the outer layer increases. Thus, since the surface of the resultant substrate becomes uneven, a fine circuit pattern cannot be formed.
When different materials such as a rigid wiring substrate and a flexible wiring substrate are integrated, if the drilling process and the plating process (pre-processes) are performed in the same condition, the states of the PTHs differ between these materials. Thus, the reliability of the connections of the layers with the PTHs deteriorates.
Conventionally, flexible substrates are laminated in for example the following manner. Holes are formed in the material of a flexible substrate such as polyimide film on which a conductive layer such as copper foil is formed from the film side by laser radiating process, photo-etching process, or the like. The holes are filled with a conductive substance such as conductive paste. Alternatively, the holes are plated. The resultant substrates are laminated with adhesive agent.
FIG. 13 is a schematic diagram for explaining a conventional laminating method of flexible substrates. Copper-clad substrate materials of which copper foil is adhered to flexible insulation layers 91a and 91b such as polyimide film are prepared. Wiring patterns 92 including via lands 92a are formed on the substrate materials by photo-etching process or the like.
Holes are formed at positions of which the insulation layers 91a and 91b are connected by laser radiating process, photo-etching process, or the like. The holes are filled with conductive paste 93 such as solder paste. The wiring patterns 92 are formed on both surfaces of a portion that is finally exposed (for example, the insulation layer 91). The resultant substrates are laminated with adhesive agent 94.
FIG. 14 is a schematic diagram for explaining another conventional laminating method of flexible substrates. In this example, a copper layer 96 is plated on an inner surface of through-hole. A gold layer 97 is plated in the through-hole on the reverse side of the wiring layer 95.
In addition, a land portion 95 that is a laminate of a copper layer 95a and a tin layer 95b is formed on the through-hole on the side of the wiring layer 95. The resultant substrates are laminated with Au--Sn eutectic solder of the gold layer 97 and the tin layer 95b.
However, in such a method, the through-hole should be filled with a conductive substance such as conductive paste 93 so as to connect layers. Alternatively, a conductive layer should be formed by plating process. Thus, the yield becomes low. Particularly, in the method shown in FIG. 14, different plating processes should be performed on both sides of the through-hole. Consequently, the yield becomes very low.
In addition, the material that bonds flexible substrates does not absorb the thickness of the via land 92a and the wiring pattern 92. Thus, the laminate wiring board becomes uneven due to the unevenness of the wiring pattern 92 that includes the via land 92a disposed on the insulation layers 91a and 91b made of the polyimide film.
In the case that the coplanarity of the wiring board due to the unevenness of an inner layer deteriorates, when a semiconductor device is mounted by flip-chip bonding method, the connecting reliability deteriorates.